1. Field of the Invention
The present invention relates to instruction pipelining and more specifically to determining the maximum achievable load-use separation (“modeled load latency”) of pipelined instructions.
2. Description of the Related Art
Generally, when certain types of instructions are scheduled for execution on a processor, it is desirable to obtain an instruction schedule that exhibits large load latencies, i.e., a schedule which tends to maximize distances (in modeled cycles) between load type instructions' use of data loaded thereby. However, when such load latencies are high, register utilization can increase dramatically. As a result, usage of instruction scheduling prevents a compiler from allocating registers for all live ranges of pipelined instructions.
As processor chips become faster, higher latencies of live ranges of pipelined instructions make it more difficult to maintain instruction level parallelism. A compiler typically determines the maximum load latency for which the available registers can be allocated. However, it is time consuming and harder for a compiler to find an acceptable maximum load latency with which all the live ranges of pipelined instruction can have efficient register allocation. A method and apparatus is needed to determine maximum acceptable load latency for which registers can be allocated.